Typically, III-N material based transistors are used for high voltage and high frequency applications. III-N material based devices may be candidates for system-on-chips (“SoCs”) applications, for example for power management integrated circuits (“ICs”) and radio frequency (“RF”)-power amplifiers. Generally, co-integration of III-N material based devices with a silicon (“Si”) substrate however is a great challenge due to dissimilar properties of the III-N materials and silicon. For example, the lattice mismatch between a GaN material and a Si wafer along <100> crystallographic orientation is about 41%. A large lattice mismatch between the III-N material and silicon typically results in high defect densities in the III-N material grown on Si. For example, the mismatch in thermal expansion coefficient between GaN and Si is about 116%. A large mismatch in thermal expansion coefficient between the III-N material and Si typically results in surface cracks on the III-N material grown on Si. These defects significantly reduce the mobility of carriers (e.g., electrons, holes, or both) in the III-N materials and can also result in poor yield and reliability issues
Currently, growth of the III-N material on Si (100) wafer requires thick and complex buffer layers. Typically, the III-N material is formed on the thick and complex buffer layers by a blanket epitaxial growth process over the entire Si wafer. The blanket epitaxial growth process is not selective area or pattern specific. The blanket approach does not allow for co-integration of both Si Complementary Metal Oxide Semiconductor (“CMOS”) circuits and III-N based devices side by side on the die. Additionally, the growth of the thick and complex buffer layers requires a lot of time that may not be suitable for high volume production.
As such, the existing techniques do not provide a pathway for co-integration of both III-N transistors and Si Complementary Metal Oxide Semiconductor (“CMOS”) circuits.